The Peripheral Component Interconnect Express (PCI Express™ (PCIe™)) protocol in accordance with links based on the PCI Express™ Specification Base Specification version 2.0 (published Jan. 17, 2007) (hereafter the PCIe™ Specification) is a computer expansion bus standard that offers many improvements over the prior bus standards. These improvements include input/output (I/O) hardware virtualization, higher maximum system bus throughput, lower I/O pin count and smaller physical footprint, better performance-scaling for bus devices, and detailed error detection and reporting mechanisms. The PCIe electrical interface is used in consumer, server, and industrial applications, to link motherboard-mounted peripherals as a passive backplane interconnect and as an expansion card interface for optional expansion components.
The PCIe bus serves as the primary motherboard-level interconnect, connecting the host system processor with both integrated peripherals and add-on peripherals (expansion cards.) In most computing systems, the PCIe bus co-exists with one or more legacy buses.
Older interface bus clocking schemes limit the bus clock to the slowest peripheral on the bus (regardless of the devices involved in the bus transaction). In contrast, the PCIe bus link supports full-duplex communication between any two endpoints, with no inherent limitation on concurrent access across multiple endpoints.
The PCIe bus protocol encapsulates communications within packets. The work of packetizing and de-packetizing data and status-message traffic is handled by the transaction layer of the PCIe port. PCIe devices communicate via logical connections or link. A link is a point-to-point communication channel between two PCIe ports, allowing both to send/receive ordinary PCI-requests and interrupts. At the physical level, a link is composed of 1 or more lanes. Low-speed peripherals use a single-lane (×1) link, while high speed peripherals, such as a graphics card, typically uses a much wider multi-lane link.